# SPI 6: Signalling

**URL:** https://discourse.securinghardware.com/t/spi-6-signalling/31
**Category:** APA #1: Embedded & IoT Systems
**Created:** [March 31, 2021, 11:27pm UTC](https://discourse.securinghardware.com/t/spi-6-signalling/31 "2021-03-31T23:27:06Z")
**Posts on this page:** 3
**Page:** 1

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### Author: ![db9923](https://discourse.securinghardware.com/letter_avatar_proxy/v4/letter/d/e5b9ba/32.png) [@db9923](https://discourse.securinghardware.com/u/db9923)
#### Post date: [March 31, 2021, 11:27pm UTC](https://discourse.securinghardware.com/t/spi-6-signalling/31/1 "2021-03-31T23:27:06Z")

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Question 6.1. in this section says: Examine the later parts of the capture data. Do they look like SPI? Why or why not?

The walk through did not answer this question. I see non-SPI traffic in my logical analyzer but I don’t understand why that would occur. Is that just random noise on the line when the chip is not in use or is something else sharing and using the same bus?

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### Author: ![joefitz](https://discourse.securinghardware.com/letter_avatar_proxy/v4/letter/j/838e76/32.png) [@joefitz](https://discourse.securinghardware.com/u/joefitz)
#### Post date: [April 1, 2021, 4:17pm UTC](https://discourse.securinghardware.com/t/spi-6-signalling/31/2 "2021-04-01T16:17:52Z")

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Thanks for asking - i’ll look at clarifying that in the lab and make sure i add that next time i’m revising the walkthrough video.

There’s two things that happen later on in the SPI capture.

At first, we’re loading the bootloader using simple fixed 32-bit memory-mapped accesses at low speed. When it’s time to load the kernel, we want that to happen faster, so the SoC will do a faster bulk read from the SPI flash chip. I don’t recall how fast, but i believe it reads at 25Mbps, which is faster than our logic analyzer can capture reliably. The result is partial data - sometimes we see nothing, sometimes it looks like random 1s and 0s, and sometimes (usually when we capture at a integer fraction of the actual data rate) we see strange patterns that don’t appear to make sense

Finally, the kernel loads and the system boots. Here, there’s a dedicated SPI controller driver, that turns the SPI flash chip into QSPI mode - quad spi. This uses DI, DO, WP and HOLD all as data lines, all at higher speed, to get 4x the throughput Pulseview does have a qspi decoder now, but again, we would need to sample tons of data to analyze that fully.

-joe

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### Author: ![db9923](https://discourse.securinghardware.com/letter_avatar_proxy/v4/letter/d/e5b9ba/32.png) [@db9923](https://discourse.securinghardware.com/u/db9923)
#### Post date: [April 1, 2021, 4:53pm UTC](https://discourse.securinghardware.com/t/spi-6-signalling/31/3 "2021-04-01T16:53:20Z")

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Thanks, that makes a lot of sense.
