SPI 5/6: Just wondered why we can't boot

Why won’t the system boot fully with the SPI clips attached? Is there a way around this?

I did a bit of investigation, and you can boot the system fine with 1, 2 and 5 connected, but attaching a probe to the clock messes things up.

I booted the system with 1, 2 and 5 connected and a disconnected probe on 6 and everything worked fine but you can’t properly decode the SPI without the clock (probably could decode some of it if you really wanted to). I then connected a BitMagic wire to the empty probe on the clock and the data returned from the flash chip was all corrupted.

cat /dev/mtd0 gave just wrong data (you can see it with BitMagic at 24MHz) and cat /overlay/upper/something gave

jffs2: Node CRC ffffffff != calculated CRC 35334158 for node at 004a6504
cat: read error: Input/output error

Anyway, I guess the clock is just super sensitive so things work in low-speed mode, but not in quad-speed mode. Maybe a different logic analyzer would work?

The SoC Starts by reading the SPI flash chip at low speeds - this should be no problem. Once it speeds up, the long logic analyzer wires are just too much of a load on the circuit for the clock to accurately propagate from the SoC to the SPI flash chip.

Clock is the most sensitive signal. It has to go low then high, once per data bit, therefore it’s always toggling twice as fast as the fastest possible data signal.
Also, if even a single clock bit is missed, all your data gets garbled. But if a single data bit is missed, then in many cases things can continue running until the potentially silent data error is hit.

If you did want to capture the entire spi transaction you’d need a few things:

  • faster logic analyzer. The spi flash chips are going up to 25mbps, meaning clock is going up or down 50M times per second, so you really want a 100mbps logic analyzer
  • shorter, better probe wires. Bitmagic is designed for lower speeds - if you want to minimize the load on your system, you want the whole probe wiring system to be short and shielded.
  • Higher-impedance logic analyzer inputs. Again, fine for lower speeds, but as you get higher speed you need your logic analyzer to ‘sense’ signals faster - meaning you want to read a ‘1’ or ‘0’ while requiring the fewest possible electrons to be diverted from the SoC-Flash communication.


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