Please confirm if my understanding of this section is correct. SPI is a low level protocol that just defines how bits move across the wire. There is another separate protocol layered on top of SPI for flash storage which defines conventions for reading and writing to memory addresses such as “0x30 + Address” for a read. Is this optional higher level protocol chip specific or is it a general standard across all SPI flash chips?
You can see this in how PulseView organizes it protocol analyzers. The SPI analyzer just finds the spots when Spi Select is asserted, and grabs the 1’s and 0’s at each clock pulse. There’s no assumptions on data direction, how many bits, MSB vs LSB or byte alignment, thought most implementations at least use 8 bit bytes of data.
You can ‘stack’ a protocol on top of the SPI analysis to look at the SPI Flash protocol. This is not officially standardized, but it’s a safe bet that nearly any chip that claims to be ‘spi flash’ and has a part number containing 25 is probably going to have an identical pinout and support the same flash protocol. Manufacturers do this so their chips can be drop-in (both hardware and software) replacements for any other manufacturers.
it’s a safe bet that nearly any chip that claims to be ‘spi flash’ and has a part number containing 25 is probably going to have an identical pinout and support the same flash protocol
Thanks. That insight from your experience with lots of these chips was exactly what I was hoping to get.