My understanding is that the whole reason we have to force the MCU into a reset state is because we are powering the board and when the board is powered the MCU will try to control the SPI flash chip. The reason we are powering the board to begin with is because you said that the chips might not be isolated so powering the flash storage will probably mean powering the MCU which gets messy. For work I am regularly soldering temporary wires (CLK, CMD, D0, VCC, VCCq, GND) to in circuit eMMC storage on mobile phones in order to dump the flash without powering on the phone. Am I just getting lucky each time with the SoC not fighting for control of the flash storage or is the messiness you refer to only applicable to SPI flash storage?
Short answer, yes, you’re getting lucky.
The longer answer is that the more complicated the system, the more power domains you’ll encounter, and the more protection checks the devices will have in place.
Mobile phones have high performance power-consuming cores as well as lower power efficient cores. They run at different voltage levels to manage battery life. The result is that lots of these systems have specific voltage supplies for each part of the system. When you power the EMMC you’re less likely to have other devices connected to the same power supply.
More complicated CPUs and higher level protocols also have lots of safety checks built in. If the CPU powers on and tries to communicate with EMMC but gets back garbage, it might just disconnect those pins. Likewise, if it tries to talk to the EMMC and needs to compete with another device driving a different signal, it might hit an over-current condition and shut down those I/O pins to save the CPU. These features are not too expensive to implement in silicon, and are generally well worth the cost in the number of expensive chips they save from getting fried.